With the increasingly high performance of super-LSI devices in the field of semiconductor manufacturing, limits are rapidly being reached in terms of both high integration and high speed in techniques of micronization on extension of the prior art. This situation has spurred development of techniques for high integration in the vertical direction as well, i.e. multilayering of wirings, as micronization of semiconductor elements continues to advance.
CMP technique is one of the most important techniques used in processes for production of devices with multilayered wiring. CMP technique is a technique in which a thin-film is formed on a substrate by chemical vapor deposition (CVD) or the like, and then the surface is flattened. For example, CMP treatment is indispensable for ensuring focal depth for lithography. When convexo-concave is present on a substrate surface, inconveniences arise as focusing becomes impossible in the exposure step or fine wiring structures cannot be sufficiently formed. CMP technique is also applied in device manufacturing steps, such as steps of forming device isolation regions by polishing of plasma oxide films (BPSG, HDP-SiO2, p-TEOS), steps of forming interlayer insulating films, or steps of flattening plugs (such as Al or Cu plugs) after embedding silicon oxide-containing films in metal wirings.
CMP is usually carried out using an apparatus that can supply a polishing solution onto a polishing pad. A substrate surface is polished by pressing the substrate against the polishing pad while supplying the polishing solution between the substrate surface and polishing pad. High performance polishing solutions is one of the essential technology for CMP technology, and various polishing solutions have been developed to date (see Patent document 1, for example).